Folded Cascode Op-Amp

A unity-gain-stable, single-stage folded cascode operational amplifier designed from scratch and simulated in PSpice. Every transistor was sized by hand using gm/Id design charts to hit gain, phase margin, and slew rate targets at low bias current.

• Achieve DC differential gain above 70 dB
• Maintain phase margin above 60° at the unity-gain frequency
• Meet a slew rate target of 25.2 V/µs
• Maximize gain–bandwidth product while minimizing bias current

• Sized all 16 MOSFETs (W and L) from the target slew rate and a gm/Id of ~20 V⁻¹ on the input pair
• Split gain evenly between the PMOS input stage and NMOS common-gate stage, with intrinsic gain ~2× each stage's share
• Built a PMOS cascode current mirror load (L = 2× the cascode devices) with V_GS = 1 V for near-zero output offset
• Ran DC operating point, AC, CMRR, and transient simulations, iterating widths until specs closed
• Verified the amplifier as a unity-gain buffer with a 0.5 V pulse input
• Benchmarked against a two-stage op-amp from an earlier assignment: matched GBW (27.9 vs 27.8 MHz) and gained ~4.4 dB of DC gain with no compensation network, at 2.6× the supply current

Slew rate landed about 7% under target; all other specs were met.